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FIN24AC PSerDes 22-Bit Bi-Directional Serializer/Deserializer
September 2005 Revised December 2005
FIN24AC PSerDes 22-Bit Bi-Directional Serializer/Deserializer
General Description
The FIN24AC PSerDes is a low power Serializer/Deserializer (SerDes) that can help minimize the cost and power of transferring wide signal paths. Through the use of serialization, the number of signals transferred from one point to another can be significantly reduced. Typical reduction is 4:1 to 6:1 for unidirectional paths. For bi-directional operation, using half duplex for multiple sources, it is possible to increase the signal reduction to close to 10:1. Through the use of differential signaling, shielding and EMI filters can also be minimized, further reducing the cost of serialization. The differential signaling is also important for providing a noise-insensitive signal that can withstand radio and electrical noise sources. Major reduction in power consumption allows minimal impact on battery life in ultra-portable applications. A unique word boundary technique assures that the actual word boundary is identified when the data is deserialized. This guarantees that each word is correctly aligned at the deserializer on a word by word basis through a unique sequence of clock and data that is not repeated except at the word boundary. It is possible to use a single PLL for most applications including bi-directional operation.
Features O Low power for minimum impact on battery life
* Multiple power-down modes * AC coupling with DC balance
O 100nA in standby mode
5mA typical operating conditions
O Cable reduction: 25:4 or greater O Bi-directional operation 50:7 reduction or greater O Differential signaling:
* 90dBm EMI when using CTL in lab conditions using a near field probe * Minimized shielding * Minimized EMI filter * Minimum susceptibility to external interference
O Up to 22 bits in either direction O Up to 20MHz parallel interface operation O Voltage translation from 1.65V to 3.6V O Ultra-small and cost-effective packaging O High ESD protection: !8kV HBM O Parallel I/O power supply (VDDP) range between
1.65V to 3.6V
Applications O Micro-controller or Pixel interfaces O Image sensors O Small displays
LCD, cell phone, digital camera, portable gaming, printer, PDA, video camera, automotive
Ordering Code:
Order Number
FIN24ACGFX FIN24ACMLX
Package Number
BGA042A MLP040A
Package Description
Pb-Free 42-Ball Ultra Small Scale Ball Grid Array (USS-BGA), JEDEC MO-195, 3.5mm Wide Pb-Free 40-Terminal Molded Leadless Package (MLP), Quad, JEDEC MO-220, 6mm Square
Pb-Free package per JEDEC J-STD-020B. BGA and MLP packages available in Tape and Reel only.
PSerDes is a trademark of Fairchild Semiconductor Corporation.
(c) 2005 Fairchild Semiconductor Corporation
DS500910
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FIN24AC
Functional Block Diagram
Connection Diagrams
Terminal Assignments for MLP Terminal Assignments for PBGA
(Top View)
(Top View)
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FIN24AC
Terminal Description
Terminal Name
DP[1:20] DP[21:22] DP[23:24] CKREF STROBE CKP DSO / DSI DSO / DSI
I/O Type
I/O I O IN IN OUT DIFF-I/O
Number of Terminals
20 2 2 1 1 1 2
Description of Signals
LVCMOS Parallel I/O. Direction controlled by DIRI pin LVCMOS Parallel Unidirectional Inputs LVCMOS Unidirectional Parallel Outputs LVCMOS Clock Input and PLL Reference LVCMOS Strobe Signal for Latching Data into the Serializer LVCMOS Word Clock Output CTL Differential Serial I/O Data Signals (Note 1) DSO: Refers to output signal pair DSI: Refers to input signal pair DSO(I): Positive signal of DSO(I) pair DSO(I): Negative signal of DSO(I) pair CTL Differential Deserializer Input Bit Clock CKSI: Refers to signal pair CKSI: Positive signal of CKSI pair CKSI: Negative signal of CKSI pair CTL Differential Serializer Output Bit Clock CKSO: Refers to signal pair CKSO: Positive signal of CKSO pair CKSO: Negative signal of CKSO pair LVCMOS Mode Selection terminals used to select Frequency Range for the RefClock, CKREF LVCMOS Control Input Used to control direction of Data Flow: DIRI = "1" Serializer, DIRI = "0" Deserializer LVCMOS Control Output Inversion of DIRI Power Supply for Parallel I/O and Translation Circuitry Power Supply for Core and Serial I/O Power Supply for Analog PLL Circuitry Use Bottom Ground Plane for Ground Signals
CKSI, CKSI
DIFF-IN
2
CKSO, CKSO
DIFF-OUT
2
S1 S2 DIRI
IN IN IN
1 1 1
DIRO VDDP VDDS VDDA GND
OUT Supply Supply Supply Supply
1 1 1 1 0
Note 1: The DSO/DSI serial port pins have been arranged such that when one device is rotated 180 degrees with respect to the other device the serial connections will properly align without the need for any traces or cable signals to cross. Other layout orientations may require that traces or cables cross.
PBGA Terminal Assignments
1
A B C D E F J DP[9] DP[11] CKP DP[13] DP[15] DP[17] DP[19]
2
DP[7] DP[10] DP[12] DP[14] DP[16] DP[18] DP[20]
3
DP[5] DP[6] DP[8] VDDP GND DP[21] DP[22]
4
DP[3] DP[2] DP[4] GND VDDS VDDA DP[23]
5
DP[1] STROBE CKSO DSO / DSI CKSI S2 DP[24]
6
CKREF DIRO CKSO DSO / DSI CKSI DIRI S1
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FIN24AC
Control Logic Circuitry
The FIN24AC has the ability to be used as a 24-bit Serializer or a 24-bit Deserializer. Pins S1 and S2 must be set to accommodate the clock reference input frequency range of the serializer. The table below shows the pin programming of these options based on the S1 and S2 control pins. The DIRI pin controls whether the device is a serializer or a deserializer. When DIRI is asserted LOW, the device is configured as a deserializer. When the DIRI pin is asserted HIGH, the device will be configured as a serializer. Changing the state on the DIRI signal will reverse the direction of the I/O signals and generate the opposite state signal on DIRO. For unidirectional operation the DIRI pin should be hardwired to the HIGH or LOW state and the DIRO pin should be left floating. For bi-directional operation the DIRI of the master device will be driven by the system and the DIRO signal of the master will be used to drive the DIRI of the slave device. Serializer/Deserializer with Dedicated I/O Variation The serialization and deserialization circuitry is setup for 24 bits. Because of the dedicated inputs and outputs only 22 bits of data are ever serialized or deserialized. Regardless of the mode of operation the serializer is always sending 24 bits of data plus 2 boundary bits and the deserializer is always receiving 24 bits of data and 2 word boundary bits. Bits 23 and 24 of the serializer will always contain the value of zero and will be discarded by the deserializer. DP[21:22] input to the serializer will be deserialized to DP[23:24] respectively. Turn-Around Functionality The device passes and inverts the DIRI signal through the device asynchronously to the DIRO signal. Care must be taken by the system designer to insure that no contention occurs between the deserializer outputs and the other devices on this port. Optimally the peripheral device driving the serializer should be put into a HIGH Impedance state prior to the DIRI signal being asserted. When a device with dedicated data outputs turns from a deserializer to a serializer the dedicated outputs will remain at the last logical value asserted. This value will only change if the device is once again turned around into a deserializer and the values are overwritten. TABLE 1. Control Logic Circuitry
Power-Down Mode: (Mode 0)
Mode 0 is used for powering down and resetting the device. When both of the mode signals are driven to a LOW state the PLL and references will be disabled, differential input buffers will be shut off, differential output buffers will be placed into a HIGH impedance state, LVCMOS outputs will be placed into a HIGH impedance state and LVCMOS inputs will be driven to a valid level internally. Additionally all internal circuitry will be reset. The loss of CKREF state is also enabled to insure that the PLL will only power-up if there is a valid CKREF signal. In a typical application mode signals of the device will typically not change states other than between the desired frequency range and the power-down mode. This allows for system level power-down functionality to be implemented via a single wire for a SerDes pair. The S1 and S2 selection signals that have their operating mode driven to a "logic 0" should be hardwired to GND. The S1 and S2 signals that have their operating mode driven to a "logic 1" should be connected to a system level power-down signal.
Serializer Operation Mode
The serializer configurations are described in the following sections. The basic serialization circuitry works essentially identically in these modes, but the actual data and clock streams will differ depending on if CKREF is the same as the STROBE signal or not. When it is stated that CKREF = STROBE this means that the CKREF and STROBE signals have an identical frequency of operation but may or may not be phase aligned. When it is stated that CKREF does not equal STROBE then each signal is distinct and CKREF must be running at a frequency high enough to avoid any loss of data condition. CKREF must never be a lower frequency than STROBE. Serializer Operation: (Figure 1) Modes 1, 2, or 3 DIRI equals 1 CKREF equals STROBE The PLL must receive a stable CKREF signal in order to achieve lock prior to any valid data being sent. The CKREF signal can be used as the data STROBE signal provided that data can be ignored during the PLL lock phase. Once the PLL is stable and locked the device can begin to capture and serialize data. Data will be captured on the rising edge of the STROBE signal and then serialized. The serialized data stream is synchronized and sent source synchronously with a bit clock with an embedded word boundary. When operating in this mode the internal deserializer circuitry is disabled including the serial clock, serial data input buffers, the bi-directional parallel outputs and the CKP word clock. The CKP word clock will be driven HIGH. Serializer Operation: (Figure 2) DIRI equals 1 CKREF does not equal STROBE If the same signal is not used for CKREF and STROBE, then the CKREF signal must be run at a higher frequency than the STROBE rate in order to serialize the data correctly. The actual serial transfer rate will remain at 26 times the CKREF frequency. A data bit value of zero will be sent when no valid data
Mode S2 Number
0 1 0 0 0 2 1 1 3 1 1
S1 DIRI
0 1 1 0 0 1 1 x 1 0 1 0 1 0
Description
Power-Down Mode 24-Bit Serializer 2MHz to 5MHz CKREF 24-Bit Deserializer 24-Bit Serializer 5MHz to 15MHz CKREF 24-Bit Deserializer 24-Bit Serializer 10MHz to 20MHz CKREF 24-Bit Deserializer
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FIN24AC
is present in the serial bit stream. The operation of the serializer will otherwise remain the same. The exact frequency that the reference clock needs to run at will be dependent upon the stability of the CKREF and STROBE signal. If the source of the CKREF signal implements spread spectrum technology then the maximum frequency of this spread spectrum clock should be used in calculating the ratio of STROBE frequency to the CKREF frequency. Similarly if the STROBE signal has significant cycle-to-cycle variation then the maximum cycle-to-cycle time needs to be factored into the selection of the CKREF frequency.
Serializer Operation: (Figure 3) DIRI equals 1 No CKREF A third method of serialization can be done by providing a free running bit clock on the CKSI signal. This mode is enabled by grounding the CKREF signal and driving the DIRI signal HIGH. At power-up the device is configured to accept a serialization clock from CKSI. If a CKREF is received then this device will enable the CKREF serialization mode. The device will remain in this mode even if CKREF is stopped. To re-enable this mode the device must be powered down and then powered back up with a "logic 0" on CKREF.
FIGURE 1. Serializer Timing Diagram (CKREF equals STROBE)
FIGURE 2. Serializer Timing Diagram (CKREF does not equal STROBE)
FIGURE 3. Serializer Timing Diagram Using Provided Bit Clock (No CKREF)
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FIN24AC
Deserializer Operation Mode
The operation of the deserializer is only dependent upon the data received on the DSI data signal pair and the CKSI clock signal pair. The following two sections describe the operation of the deserializer under two distinct serializer source conditions. References to the CKREF and STROBE signals refer to the signals associated with the serializer device used in generating the serial data and clock signals that are inputs to the deserializer. When operating in this mode the internal serializer circuitry is disabled including the parallel data input buffers. If there is a CKREF signal provided then the CKSO serial clock will continue to transmit bit clocks. Upon device power-up (S1 or S2 = 1) all deserializer output data pins will be driven low until valid data is passed through the deserializer. Deserializer Operation: DIRI equals 0 (Serializer Source: CKREF equals STROBE) When the DIRI signal is asserted LOW the device will be configured as a deserializer. Data will be captured on the serial port and deserialized through use of the bit clock sent with the data. The word boundary is defined in the actual clock and data signal. Parallel data will be generated at the time the word boundary is detected. The falling edge of CKP will occur approximately 6 bit times after the falling edge of CKSI. The rising edge of CKP will go high approximately 13 bit times after CKP goes LOW. The rising edge of CKP will be generated approximately 13 bit times later. When no embedded word boundary occurs then no pulse on CKP will be generated and CKP will remain HIGH. Deserializer Operation: DIRI equals 0 (Serializer Source: CKREF does not equal STROBE) The logical operation of the deserializer remains the same regardless of if the CKREF is equal in frequency to the STOBE or at a higher frequency than the STROBE. The actual serial data stream presented to the deserializer will however be different because it will have non-valid data bits sent between words. The duty cycle of CKP will vary based on the ratio of the frequency of the CKREF signal to the STROBE signal. The frequency of the CKP signal will be equal to the STROBE frequency. The falling edge of CKP will occur 6 bit times after the data transition. The LOW time of the CKP signal will be equal to 1/2 (13 bit times) of the CKREF period. The CKP HIGH time will be equal to STROBE period - 1/2 of the CKREF period. Figure 5 is representative of a waveform that could be seen when CKREF is not equal to STROBE. If CKREF was significantly faster then additional non-valid data bits would occur between data words.
FIGURE 4. Deserializer Timing Diagram (Serializer Source: CKREF equals STROBE)
FIGURE 5. Deserializer Timing Diagram (Serializer Source: CKREF does not equal STROBE)
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FIN24AC
Embedded Word Clock Operation
The FIN24AC sends and receives serial data source synchronously with a bit clock. The bit clock has been modified to create a word boundary at the end of each data word. The word boundary has been implemented by skipping a low clock pulse. This appears in the serial clock stream as 3 consecutive bit times where signal CKSO remains HIGH. In order to implement this sort of scheme two extra data bits are required. During the word boundary phase the data will toggle either HIGH-thenLOW or LOW-then-HIGH dependent upon the last bit of the actual data word. Table 2 provides some examples showing the actual data word and the data word with the word boundary bits added. Note that a 24-bit word will be extended to 26-bits during
serial transmission. Bit 25 and Bit 26 are defined with-respect-to Bit 24. Bit 25 will always be the inverse of Bit 24, and Bit 26 will always be the same as Bit 24. This insures that a "0" o "1" and a "1" o "0" transition will always occur during the embedded word phase where CKSO is HIGH. The serializer generates the word boundary data bits and the boundary clock condition and embeds them into the serial data stream. The deserializer looks for the end of the word boundary condition to capture and transfer the data to the parallel port. The deserializer only uses the embedded word boundary information to find and capture the data. These boundary bits are then stripped prior to the word being sent out of the parallel port.
TABLE 2. Word Boundary Data Bits
24-Bit Data Words Hex
155555h xxxxxxh
24-Bit Data Word with Word Boundary Hex Binary
1FFFFFFh 01 1111 1111 1111 1111 1111 1111b
Binary
3FFFFFh 0011 1111 1111 1111 1111 1111b
0101 0101 0101 0101 01010 0101b 1155555h 01 0101 0101 0101 0101 0101 0101b 0xxx xxxx xxxx xxxx xxxx xxxxb 1xxxxxxh 01 0xxx xxxx xxxx xxxx xxxx xxxxb
LVCMOS Data I/O
The LVCMOS input buffers have a nominal threshold value equal to 1/2 of VDDP. The input buffers are only operational when the device is operating as a serializer. When the device is operating as a deserializer the inputs are gated off to conserve power. The LVCMOS 3-STATE output buffers are rated for a source/ sink current of 2 mAs at 1.8V. The outputs are active when the DIRI signal is asserted LOW. When the DIRI signal is asserted HIGH the bi-directional LVCMOS I/Os will be in a HIGH-Z state. Under purely capacitive load conditions the output will swing between GND and VDDP. Unused LVCMOS input buffers must be tied off to either a valid logic LOW or a valid logic HIGH level to prevent static current draw due to a floating input. Unused LVCMOS output should be left floating. Unused bi-directional pins should be connected to GND through a high value resistor. If a FIN24AC device is configured as an unidirectional serializer then unused data I/O can be treated as unused inputs. If the FIN24AC is hardwired as a deserializer then unused data I/O can be treated as unused outputs.
Differential I/O Circuitry
The FIN24AC employs FSC proprietary CTL I/O technology. CTL is a low power, low EMI differential swing I/O technology. The CTL output driver generates a constant output source and sink current. The CTL input receiver senses the current difference and direction from the corresponding output buffer to which it is connected. This differs from LVDS which uses a constant current source output but a voltage sense receiver. Like LVDS an input source termination resistor is required to properly terminate the transmission line. The FIN24AC device incorporates an internal termination resistor on the CKSI receiver and a gated internal termination resistor on the DS input receiver. The gated termination resistor insures proper termination regardless of direction of data flow. The relative greater sensitivity of the current sense receiver of CTL allows it to work at much lower current drive and correspondingly a much lower voltage. During power-down mode the differential inputs will be disabled and powered down and the differential outputs will be placed in a HIGH-Z state. CTL inputs have an inherent failsafe capability that supports floating inputs. When the CKSI input pair of the serializer is unused it can reliably be left floating. Alternately both of the inputs can be connected to ground. CTL inputs should never be connected to VDD. When the CKSO output of the deserializer is unused it should be allowed to float.
FIGURE 6. LVCMOS I/O
FIGURE 7. Bi-Directional Differential I/O Circuitry
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FIN24AC
PLL Circuitry
The CKREF input signal is used to provide a reference to the PLL. The PLL will generate internal timing signals capable of transferring data at 26 times the incoming CKREF signal. The output of the PLL is a Bit Clock that is used to serialize the data. The bit clock is also sent source synchronously with the serial data stream. There are two ways to disable the PLL. The PLL can be disabled by entering the Mode 0 state (S1 = S2 = 0). The PLL will disable immediately upon detecting a LOW on both the S1 and S2 signals. When any of the other modes are entered by asserting either S1 or S2 HIGH and by providing a CKREF signal the PLL will power-up and goes through a lock sequence. One must
wait the specified number of clock cycles prior to capturing valid data into the parallel port. When the PSerDes chipset transitions from a power down state (S1, S2 = 0, 0) to a powered state (example S1, S2 = 1, 1), CKP on the deserializer will transition LOW for a short duration, and will return HIGH. Following this, the signal level of the deserializer at CKP will correspond to the serializer signal levels. An alternate way of powering down the PLL is by stopping the CKREF signal either HIGH or LOW. Internal circuitry detects the lack of transitions and shuts the PLL and serial I/O down. Internal references will not however be disabled allowing for the PLL to power-up and re-lock in a lesser number of clock cycles than when exiting Mode 0. When a transition is seen on the CKREF signal the PLL will once again be reactivated.
Application Mode Diagrams Unidirectional Data Transfer
FIGURE 8. Simplified Block Diagram for Unidirectional Serializer and Deserializer
Figure 8 shows the basic operation diagram when a pair of SerDes is configured in an unidirectional operation mode. Master Operation: The device will... (Please refer to Figure 8) 1. Be configured as a serializer at power-up based on the value of the DIRI signal. 2. Accept CKREF_M word clock and generate a bit clock with embedded word boundary. This bit clock will be sent to the slave device through the CKSO port. 3. Receive parallel data on the rising edge of STROBE_M. 4. Generate and transmit serialized data on the DS signals which is source synchronous with CKSO. 5. Generate an embedded word clock for each strobe signal.
Slave Operation: The device will... 1. Be configured as a deserializer at power-up based on the value of the DIRI signal. 2. Accept an embedded word boundary bit clock on CKSI. 3. Deserialize the DS Data stream using the CKSI input clock. 4. Write parallel data onto the DP_S port and generate the CKP_S. CKP_S will only be generated when a valid data word occurs.
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FIN24AC
FIGURE 9. Unidirectional Serializer and Deserializer
FIGURE 10. Multiple Units, Unidirectional Signals in Each Direction
Figure 10 shows a half duplex connectivity diagram. This connectivity allows for two unidirectional data streams to be sent across a single pair of SerDes devices. Data will be sent on a frame by frame basis. For this mode of operation to work there needs to be some synchronization between when the Camera sends its data frame and when the LCD sends its data. One option for this is to have the LCD send data during the camera blanking period. External logic may need to be provided in order for this mode of operation to work. Devices will alternate frames of data controlled by a direction control and a direction sense. When DIRI, on the right-hand FIN24AC is HIGH, data will be sent from the Camera to the
Camera interface at the base. When DIRI, on the right-hand FIN24AC goes LOW data will be sent from the baseband process to the LCD. The direction is then changed at DIRO on the right-hand FIN24AC indicating to the left-hand FIN24AC to change direction. Data will be sent from the Base LCD Unit to the LCD. The DIRO pin on the left-hand FIN24AC is used to indicate to the base control unit that the signals are changing direction and the LCD is now available to be sent data. DIRI on the right-hand FIN24AC could typically use a timing reference signal such as VSYNC from the camera interface to indicate direction change. A derivative of this signal may be required in order to make sure that no data is lost on the final data transfer.
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FIN24AC
Absolute Maximum Ratings(Note 2)
Supply Voltage (VDD) ALL Input/Output Voltage LVDS Output Short Circuit Duration Storage Temperature Range (TSTG) Maximum Junction Temperature (TJ) Lead Temperature (TL) (Soldering, 4 seconds) ESD Rating Human Body Model, 1.5K:, 100pF All Pins CKSO, CKSI, DSO to GND
Recommended Operating Conditions
Supply Voltage (VDDA, VDDS) Supply Voltage (VDDP) Operating Temperature (TA) (Note 2) Supply Noise Voltage (VDDA-PP) 2.5V to 2.9V 1.65V to 3.6V
0.5V to 4.6V 0.5V to 4.6V
Continuous
65qC to 150qC 150qC 260qC
30qC to 70qC
100 mVP-P
!2kV !7.5kV
Note 2: Absolute maximum ratings are DC values beyond which the device may be damaged or have its useful life impaired. The datasheet specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation outside datasheet specifications.
DC Electrical Characteristics Over supply voltage and operating temperature ranges, unless otherwise specified.
Min Symbol LVCMOS I/O VIH VIL VOH Input High Voltage Input Low Voltage Output High Voltage IOH = 2.0 mA VDDP = 3.3 r 0.3 VDDP = 2.5 r 0.2 VDDP = 1.8 r 0.15 VOL Output Low Voltage IOL = 2.0 mA VDDP = 3.3 r 0.3 VDDP = 2.5 r 0.2 VDDP = 1.8 r 0.15 IIN DIFFERENTIAL I/O IODH IODL IOZ IIZ VICM VGO Output HIGH Source Current Output LOW Sink Current Disabled Output Leakage Current Disabled Input Leakage Current Input Common Mode Range Input Voltage Ground Off-set Relative to Driver (Note 4) RTRM CKSI Internal Receiver Termination Resistor RTRM DSI Internal Receiver Termination Resistor VID = 50mV, VIC = 925mV, DIRI = 0 | CKSI - CKSI | = VID VID = 50mV, VIC = 925mV, DIRI = 0 | DSI - DSI | = VID 80.0 100 120 VOS = 1.0V, Figure 11 VOS = 1.0V, Figure 11 CKSO, DSO = 0V to VDDS, S2 = S1 = 0V CKSI, DSI = 0V to VDDS, S2 = S1 = 0V VDDS = 2.775 r 5% see Figure 12 0 V Input Current VIN = 0V to 3.6V 0.25 x VDDP V 0.75 x VDDP V 0.65 x VDDP GND VDDP 0.35 x VDDP V Parameter Test Conditions (Note 3) Typ Max Unit
5.0 1.75
0.950
5.0
PA
mA mA
r0.1 r0.1
VGO 0.80
r5.0 r5.0
PA PA
V
: :
80.0
100
120
Note 3: Typical Values are given for VDD = 2.775V and TA = 25qC. Positive current values refer to the current flowing into device and negative values means current flowing out of pins. Voltage are referenced to GROUND unless otherwise specified (except 'VOD and VOD). Note 4: VGO is the difference in device ground levels between the CTL Driver and the CTL Receiver.
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FIN24AC
Power Supply Currents
Symbol IDDA1 Parameter VDDA Serializer Static Supply Current IDDA2 VDDA Deserializer Static Supply Current IDDS1 VDDS Serializer Static Supply Current IDDS2 VDDS Deserializer Static Supply Current IDD_PD VDD Power-Down Supply Current IDD_PD = IDDA IDDS IDDP IDD_SER1 26:1 Dynamic Serializer Power Supply Current IDD_SER1 = IDDA IDDS IDDP CKREF = STROBE DIRI = H See Figure 13 Test Conditions All DP and Control Inputs at 0V or VDD NOCKREF, S2 = 0, S1 = 1, DIR = 1 All DP and Control Inputs at 0V or VDD NOCKREF, S2 = 0, S1 = 1, DIR = 0 All DP and Control Inputs at 0V or VDD NOCKREF, S2 = 0, S1 = 1, DIR = 1 All DP and Control Inputs at 0V or VDD NOCKREF, S2 = 0, S1 = 1, DIR = 0 S1 = S2 = 0, 0.1 All Inputs at GND or VDD S2 = L S1 = H S2 = H S1 = L S2 = H S1 = H IDD_DES1 1:26 Dynamic Deserializer Power Supply Current IDD_DES1 = IDDA IDDS IDDP CKREF = STROBE DIRI = L See Figure 13 S2 = L S1 = H S2 = H S1 = L S2 = H S1 = H IDD_SER2 26:1 Dynamic Serializer Power Supply Current IDD_SER2 = IDDA IDDS IDDP NO CKREF STROBE o Active CKSI = 15X Strobe DIRI = H See Figure 13 2 MHz 5 MHz 5 MHz 15 MHz 10 MHz 20 MHz 2 MHz 5 MHz 5 MHz 15 MHz 10 MHz 20 MHz 2 MHz 5 MHz 10 MHz 15 MHz 9.0 14.0 9.5 mA 17.0 11.0 15.5 5.5 6.0 4.0 mA 5.5 7.5 10.0 8.0 8.5 mA 10.0 12.0 4.5 mA 4.0 550 Min Typ 450 Max Units
PA PA
mA
PA
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FIN24AC
AC Electrical Characteristics Over supply voltage and operating temperature ranges, unless otherwise specified.
Min Symbol Serializer Input Operating Conditions tTCP CKREF Clock Period (2 MHz - 20 MHz) See Figure 17 CKREF = STROBE S2 = 0 S2 = 1 S2 = 1 fREF CKREF Frequency Relative to Strobe Frequency CKREF does not equal STROBE tCPWH tCPWL tCLKT tSPWH fMAX CKREF Clock High Time CKREF Clock Low Time LVCMOS Input Transition Time STROBE Pulse Width HIGH/LOW Maximum Serial Data Rate See Figure 17 See Figure 17 CKREF x 26 S2 = 0 S2 = 1 S2 = 1 tSTC tHTC fREF DP(n) Setup to STROBE DP(n) Hold to STROBE CKREF Frequency Relative to Strobe Frequency DIRI = 1 see Figure 6 (f = 5MHz) CKREF Does Not Equal STROBE S1 = 1 S1 = 0 S1 = 1 (T x 4)/26 52.0 130 260 2.5 2.0 1.1 x fSTROBE 20.0 S2 = 0 S2 = 1 S2 = 1 S1 = 1 S1 = 0 S1 = 1 S1 = 1 S1 = 0 S1 = 1 0.2 0.2 0.5 0.5 90.0 (T x 22)/26 130 390 520 ns ns MHz Mb/s 1.1 *fST 200 66.0 50.0 T 500 200 100 5.0 15.0 20.0 T T ns ns MHz ns Parameter Test Conditions (Note 5) Typ Max Units
Serializer AC Electrical Characteristics tTCCD Transmitter Clock Input to Clock Output Delay tSPOS CKSO Position Relative to DS See Figure 20, DIRI = 1, CKREF = STROBE See Figure 23, (Note 6) 33a 1.5 35a 6.5 250 ns ps
50.0
PLL AC Electrical Characteristics tTPLLS0 tTPLLD0 tTPLLD1 Serializer Phase Lock Loop Stabilization Time PLL Disable Time Loss of Clock PLL Power-Down Time See Figure 19 See Figure 24 See Figure 25, (Note 7) 200 30.0 20.0
Ps Ps
ns
Deserializer Input Operation Conditions tS_DS tH_DS Serial Port Setup Time, DS-to-CKSI Serial Port Hold Time, DS-to-CKS Figure 22, (Note 8) Figure 22, (Note 8) 1.4 ns ps
250
50.0 13a-3 13a-3 8a-6 T 500 13a3 13a3 8a1
Deserializer AC Electrical Characteristics tRCOP tRCOL tRCOH tPDV Deserializer Clock Output (CKP OUT) Period CKP OUT Low Time CKP OUT High Time Data Valid to CKP LOW Figure 18 Figure 18 (Rising Edge Strobe) Serializer Source STROBE = CKREF Where a = (1/f)/26 (Note 9) Figure 18 (Rising Edge Strobe) Where a = (1/f)/26 (Note 9) tROLH tROHL Output Rise Time (20% to 80%) Output Fall time (80% to 20%) CL = 5 pF Figure 15 2.5 2.5 ns ns ns ns ns ns
Note 5: Typical Values are given for VDD = 2.775V and TA = 25qC. Positive current values refer to the current flowing into device and negative values means current flowing out of pins. Voltage are referenced to GROUND unless otherwise specified (except 'VOD and VOD). Note 6: Skew is measured form either the rising or falling edge of CKSO clock to the rising or falling edge of data (DSO). Signals are edge aligned. Both outputs should have identical load conditions for this test to be valid. Note 7: The power-down time is a function of the CKREF frequency prior to CKREF being stopped HIGH or LOW and the state of the S1/S2 mode pins. The specific number of clock cycles required for the PLL to be disabled will vary dependent upon the operating mode of the device. Note 8: Signals are transmitted from the serializer source synchronously. Note that in some cases data is transmitted when the clock remains at a high state. Skew should only be measured when data and clock are transitioning at the same time. Total measured input skew would be a combination of output skew from the serializer, load variations and ISI and jitter effects. Note 9: Rising edge of CKP will appear approximately 13 bit times after the falling edge of the CKP output. Falling edge of CKP will occur approximately 8 bit times after a data transition or 6 bit times after the falling edge of CKSO. Variation of the data with respect of the CKP signal is due to internal propagation delay differences of the data and CKP path and propagation delay differences on the various data pins. Note that if the CKREF is not equal to STROBE for the serializer then the CKP signal will not maintain a 50% duty cycle. The low time of CKP will remain 13 bit times.
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FIN24AC
Control Logic Timing Controls
Symbol tPHL_DIR, tPLH_DIR tPLZ, tPHZ tPZL, tPZH tPLZ, tPHZ tPZL, tPZH tPLZ, tPHZ tPZL, tPZH Propagation Delay DIRI LOW-to-HIGH or HIGH-to-LOW DIRI-to-DIRO Propagation Delay DIRI LOW-to-HIGH DIRI-to-DP Propagation Delay DIRI HIGH-to-LOW DIRI-to-DP Deserializer Disable Time: S0 or S1 to DP Deserializer Enable Time: S0 or S1 to DP Serializer Disable Time: S0 or S1 to CKSO, DS Serializer Enable Time: S0 or S1 to CKSO, DS DIRI = 0, 25.0 S1(2) = 0 and S2(1) = LOW-to-HIGH DIRI = 0, (Note 10) 2.0 S1(2) = 0 and S2(1) = LOW-to-HIGH DIRI = 1, 25.0 S1(2) = 0 and S2(1) = HIGH-to-LOW Figure 25 DIRI = 1, 65.0 S1(2) and S2(1) = LOW-to-HIGH Figure 25 ns ns Figure 26 Figure 26 ns 25.0 ns 25.0 ns 17.0 ns Parameter Test Conditions Min Typ Max Units
Ps
Note 10: Deserializer Enable Time includes the amount of time required for internal voltage and current references to stabilize. This time is significantly less than the PLL Lock Time and therefore will not limit overall system startup time.
Capacitance
Symbol CIN Parameter Capacitance of Input Only Signals, CKREF, STROBE, S1, S2, DIRI CIO Capacitance of Parallel Port Pins DP1:12 CIO-DIFF Capacitance of Differential I/O Signals Test Conditions DIRI = 1, S1 = S2 = 0, 2.0 VDD = 2.5V DIRI = 1, S1 = S2 = 0, 2.0 VDD = 2.5V DIRI = 0, S1 = S2 = 0, 2.0 VDD = 2.775V pF pF pF Min Typ Max Units
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FIN24AC
AC Loading and Waveforms
FIGURE 11. Differential CTL Output DC Test Circuit
FIGURE 12. CTL Input Common Mode Test Circuit
Note: The Worst Case test pattern produces a maximum toggling of internal digital circuits, CTL I/O and LVCMOS I/O with the PLL operating at the reference frequency unless otherwise specified. Maximum power is measured at the maximum VDD values. Minimum values are measured at the minimum VDD values. Typical values are measured at VDD = 2.5V.
FIGURE 13. "Worst Case" Serializer Test Pattern
FIGURE 14. CTL Output Load and Transition Times
FIGURE 15. LVCMOS Output Load and Transition Times
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FIN24AC
AC Loading and Waveforms
(Continued)
Setup: MODE0 = "0" or "1", MODE1 = "1", SER/DES = "1"
FIGURE 16. Serial Setup and Hold Time
FIGURE 17. LVCMOS Clock Parameters
Setup: EN_DES = "1", CKSI and DSI are valid signals
Note: CKREF Signal is free running.
FIGURE 18. Deserializer Data Valid Window Time and Clock Output Parameters
FIGURE 19. Serializer PLL Lock Time
Note: STROBE = CKREF
FIGURE 20. Serializer Clock Propagation Delay
FIGURE 21. Deserializer Clock Propagation Delay
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FIN24AC
AC Loading and Waveforms
(Continued)
Note: Data is typically edge aligned with clock
FIGURE 22. Differential Input Setup and Hold Times
FIGURE 23. Differential Output Signal Skew
Note: CKREF Signal can be stopped either HIGH or LOW
FIGURE 24. PLL Loss of Clock Disable Time
FIGURE 25. PLL Power-Down Time
Note: CKREF must be active and PLL must be stable
Note: If S1(2) transitioning then S2(1) must = 0 for test to be valid
FIGURE 26. Serializer Enable and Disable Time
FIGURE 27. Deserializer Enable and Disable Times
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FIN24AC
Tape and Reel Specification
BGA Embossed Tape Dimension
Dimensions are in millimeters
Package
3.5 x 4.5
A0
TBD
B0
TBD
D
1.55
D1
1.5
E r0.1
1.75
F r0.1
5.5
K0 r0.1
1.1
P1 TYP
8.0
P0
4.0
P2
2.0
T
0.3
TC
0.07
W
12.0
WC
9.3
r0.10 r0.10 r0.05 min
TYP r0/05 TYP r0.005 r0.3 TYP
Note: A0, B0, and K0 dimensions are determined with respect to the EIA/JEDEC RS-481 rotational and lateral movement requirements (see sketches A, B, and C).
Dimensions are in millimeters
Tape Width
8 12 16
Dia A max
330 330 330
Dim B min
1.5 1.5 1.5
Dia C 0.5/0.2
13.0 13.0 13.0
Dia D min
20.2 20.2 20.2
Dim N min
178 178 178
Dim W1 2.0/0
8.4 12.4 16.4
Dim W2 max
14.4 18.4 22.4
Dim W3 (LSL - USL)
7.9 a 10.4 11.9 a 15.4 15.9 a 19.4
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FIN24AC
Tape and Reel Specification (continued)
MLP Embossed Tape Dimension
Dimensions are in millimeters
Package
5x5 6x6
D1 Ao Bo D r0.10 r0.10 r0.05 min
5.35 6.30 5.35 6.30 1.55 1.55 1.5 1.5
P1 P2 E F Ko Po T Tc W Wc r0.1 r0.1 r0.1 TYP TYP r0/05 TYP r0.005 r0.3 TYP
1.75 1.75 5.5 5.5 1.4 1.4 8 8 4 4 2.0 2.0 0.3 0.3 0.07 0.07 12 12 9.3 9.3
Note: Ao, Bo, and Ko dimensions are determined with respect to the EIA / JEDEC RS-481 rotational and lateral movement requirements (see sketches A, B, and C).
Shipping Reel Dimension
Dimensions are in millimeters
Tape Width
8 12 16
Dia A max
330 330 330
Dim B min
1.5 1.5 1.5
Dia C .5/.2
13 13 13
Dia D min
20.2 20.2 20.2
Dim N min
178 178 178
Dim W1 Dim W2 .2/0 max
8.4 12.4 16.4 14.4 18.4 22.4
Dim W3 (LSL - USL)
7.9 a10.4 11.9 a 15.4 15.9 a 19.4
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18
FIN24AC
Physical Dimensions inches (millimeters) unless otherwise noted
Pb-Free 42-Ball Ultra Small Scale Ball Grid Array (USS-BGA), JEDEC MO-195, 3.5mm Wide Package Number BGA042A
19
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FIN24AC
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Pb-Free 40-Terminal Molded Leadless Package (MLP), Quad, JEDEC MO-220, 6mm Square Package Number MLP040A
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FIN24AC PSerDes 22-Bit Bi-Directional Serializer/Deserializer
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION As used herein: provided in the labeling, can be reasonably expected to result in significant injury to the user. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or 2. A critical component is any component of a life support (b) support or sustain life, or (c) whose failure to perform device or system whose failure to perform can be reasonwhen properly used in accordance with instructions for use ably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
PRODUCT STATUS DEFINITIONS
Definition of terms
Datasheet Identification Product Status
Advance Information Preliminary Formative or In Design First Production
Definition
This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains specifications on a product that has been discontinued by Fairchild Semiconductor. The datasheet is printed for reference information only.
No Identification Needed
Full Production
Obsolete
Not In Production
21
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